High voltage (HV) semiconductor devices such as diodes, transistors and insulated gate bipolar transistors usually include doped semiconductor areas so as to define a p-n junction. A p-n junction is one of the basic building blocks of semiconductor technology. In HV applications, which, in some cases, require the handling of voltages of approximately 60V and higher, the devices usually contain a dedicated pn junction, which depletes in the off-state and supports the off-state voltage, i.e. the depleted region electrically isolates the p-doped region and the n-doped region from one another. This region is called “drift region”, “lowly-doped region” or “voltage supporting region”.
Alternatively, the drift region can be replaced by alternating p and n highly doped layers that under mutual charge compensation can completely deplete in the off-state and support a high voltage across the device. These types of configurations are widely known as RESURF or SuperJunction.
The high voltage device is embedded in a semiconductor substrate or material, which is normally held at low voltage. For this reason high voltage semiconductor devices usually also contain isolation regions, which electrically isolate the device from the surrounding substrate. These isolation regions help to ensure that the high voltages are contained within the high voltage device and that the high voltage does not negatively impact the surrounding devices and package.
For lateral high voltage devices such as LDMOS, LIGBT, the lightly doped/SJ drift region should not only be isolated from the surrounding substrate but should also be terminated in such a way that the carefully engineered field or potential distribution is not altered (or that any such alteration is kept sufficiently insignificant), so that as much as possible of the full voltage rating of the HV device can be realized. In order to be effective these isolation areas should have a higher voltage carrying capability than the interior devices. In this way the voltage rating is given by the interior device only.
Electrical isolation can be achieved by dielectric materials or by reverse-biased pn-junctions. Under Dielectric Isolation, vertical isolation can be realized by using SOI (Silicon on Insulator) material, which contains a BOX (Buried Oxide) layer between the active top layer and the handle wafer substrate. Lateral isolation can be achieved by forming oxide filled trenches or field oxide reaching all the way down to the BOX.
Junction isolation normally utilises similar lowly-doped regions as the drift region of the HV device. The inventors have appreciated that the presence of a Super Junction in the drift region imposes additional challenges on the design of the device isolation.
Whether or not a Super Junction structure is present in the drift region, the inventors have appreciated that the presence of a Super Junction structure in the termination region may be useful in some devices. The presence of a Super Junction structure in the termination region may for example help to avoid breakdown in certain regions of the device, such as at an edge of the p or n-doped regions referred to above.
WO2010133923 and WO2010133525 disclose p-n junctions. Both publications are hereby incorporated by reference for all purposes in their entirety.